Adaptive concurrency for write persistence

ABSTRACT

A method for adaptive concurrency for write persistence in a storage system, performed by the storage system, is provided. The method includes selecting a write process from among a plurality of write processes, responsive to receiving a write request for writing data into the storage system, and writing the data into the storage system in accordance with the selected write process. One of the plurality of write processes includes transferring the data into the storage system, locking an inode associated with file information of the data in memory, updating the file information in the inode while the inode is locked, committing the data while the inode is locked, and unlocking the inode.

BACKGROUND

Solid-state memory, such as flash, is currently in use in solid-state drives (SSD) to augment or replace conventional hard disk drives (HDD), writable CD (compact disk) or writable DVD (digital versatile disk) drives, collectively known as spinning media, and tape drives, for storage of large amounts of data. Flash and other solid-state memories have characteristics that differ from spinning media. Yet, many solid-state drives are designed to conform to hard disk drive standards for compatibility reasons, which makes it difficult to provide enhanced features or take advantage of unique aspects of flash and other solid-state memory. A write process that works well on a hard disk drive is not necessarily optimal for writing to solid-state memory, and is not necessarily optimal for all write requests.

It is within this context that the embodiments arise.

SUMMARY

In some embodiments, a method for adaptive concurrency for write persistence in a storage system, performed by the storage system, is provided. The method includes selecting a write process from among a plurality of write processes, responsive to receiving a write request for writing data into the storage system, and writing the data into the storage system in accordance with the selected write process. One of the plurality of write processes includes transferring the data into the storage system, locking an inode associated with file information of the data in memory, updating the file information in the inode while the inode is locked, committing the data while the inode is locked, and unlocking the inode. The method may be embodied on a computer readable media and executed through a processor.

Other aspects and advantages of the embodiments will become apparent from the following detailed description taken in conjunction with the accompanying drawings which illustrate, by way of example, the principles of the described embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

The described embodiments and the advantages thereof may best be understood by reference to the following description taken in conjunction with the accompanying drawings. These drawings in no way limit any changes in form and detail that may be made to the described embodiments by one skilled in the art without departing from the spirit and scope of the described embodiments.

FIG. 1 is a perspective view of a storage cluster with multiple storage nodes and internal storage coupled to each storage node to provide network attached storage, in accordance with some embodiments.

FIG. 2 is a block diagram showing an interconnect switch coupling multiple storage nodes in accordance with some embodiments.

FIG. 3 is a multiple level block diagram, showing contents of a storage node and contents of one of the non-volatile solid state storage units in accordance with some embodiments.

FIG. 4 shows a storage server environment, which uses embodiments of the storage nodes and storage units of FIGS. 1-3 in accordance with some embodiments.

FIG. 5 is a blade hardware block diagram, showing a control plane, compute and storage planes, and authorities interacting with underlying physical resources, in accordance with some embodiments.

FIG. 6 depicts elasticity software layers in blades of a storage cluster, in accordance with some embodiments.

FIG. 7 depicts authorities and storage resources in blades of a storage cluster, in accordance with some embodiments.

FIG. 8 shows a write process selector that selects a process from among multiple write processes, to satisfy a data write request, in accordance with some embodiments.

FIG. 9 depicts multiple write processes, suitable for use in the write process selector of FIG. 8.

FIG. 10 shows an inode with a lock, suitable for use in the write processes of FIGS. 8 and 9.

FIG. 11 depicts a file extent lookaside as a data structure suitable for use with the write processes of FIGS. 8 and 9.

FIG. 12 is a flow diagram of a method for adaptive concurrency for write persistence, which can be practiced in the storage cluster of FIGS. 1-7, using the write process selector of FIGS. 8-11, in accordance with some embodiments.

FIG. 13 is an illustration showing an exemplary computing device which may implement the embodiments described herein.

DETAILED DESCRIPTION

A storage system, in various embodiments described herein, has a write process selector that selects among multiple write processes to optimize writing for different write requests. Among the possibilities for write processes are writing data to NVRAM (non-volatile random-access memory), for later flushing to flash memory in a background write process, writing to NVRAM outside of an inode lock, with the inode updated and the data committed while the inode is locked, and writing directly to flash memory and bypassing NVRAM, outside of an inode lock, with the inode updated and the data committed while the inode is locked. Selection of a write process is based on whether the data is a small or large amount relative to a threshold, or whether the data is arriving in series or in parallel, since different write processes have different efficiencies in these circumstances. The write processes use locks so that I nodes of the files are kept coherent while concurrent writing is occurring across storage nodes and solid-state storage units. Data is persisted through write commits. Selection among multiple write processes that can operate concurrently in different storage nodes and storage units across the storage cluster while persisting data imbues the system with adaptive concurrency for write persistence.

The embodiments below describe a storage cluster that stores user data, such as user data originating from one or more user or client systems or other sources external to the storage cluster. The storage cluster distributes user data across storage nodes housed within a chassis, using erasure coding and redundant copies of metadata. Erasure coding refers to a method of data protection or reconstruction in which data is stored across a set of different locations, such as disks, storage nodes or geographic locations. Flash memory is one type of solid-state memory that may be integrated with the embodiments, although the embodiments may be extended to other types of solid-state memory or other storage medium, including non-solid state memory. Control of storage locations and workloads are distributed across the storage locations in a clustered peer-to-peer system. Tasks such as mediating communications between the various storage nodes, detecting when a storage node has become unavailable, and balancing I/Os (inputs and outputs) across the various storage nodes, are all handled on a distributed basis. Data is laid out or distributed across multiple storage nodes in data fragments or stripes that support data recovery in some embodiments. Ownership of data can be reassigned within a cluster, independent of input and output patterns. This architecture described in more detail below allows a storage node in the cluster to fail, with the system remaining operational, since the data can be reconstructed from other storage nodes and thus remain available for input and output operations. In various embodiments, a storage node may be referred to as a cluster node, a blade, or a server. Various system aspects are discussed below with reference to FIGS. 1-7. A write process selector and various write processes are described with reference to FIGS. 8-12.

The storage cluster is contained within a chassis, i.e., an enclosure housing one or more storage nodes. A mechanism to provide power to each storage node, such as a power distribution bus, and a communication mechanism, such as a communication bus that enables communication between the storage nodes are included within the chassis. The storage cluster can run as an independent system in one location according to some embodiments. In one embodiment, a chassis contains at least two instances of both the power distribution and the communication bus which may be enabled or disabled independently. The internal communication bus may be an Ethernet bus, however, other technologies such as Peripheral Component Interconnect (PCI) Express, InfiniBand, and others, are equally suitable. The chassis provides a port for an external communication bus for enabling communication between multiple chassis, directly or through a switch, and with client systems. The external communication may use a technology such as Ethernet, InfiniBand, Fibre Channel, etc. In some embodiments, the external communication bus uses different communication bus technologies for inter-chassis and client communication. If a switch is deployed within or between chassis, the switch may act as a translation between multiple protocols or technologies. When multiple chassis are connected to define a storage cluster, the storage cluster may be accessed by a client using either proprietary interfaces or standard interfaces such as network file system (NFS), common internet file system (CIFS), small computer system interface (SCSI) or hypertext transfer protocol (HTTP). Translation from the client protocol may occur at the switch, chassis external communication bus or within each storage node.

Each storage node may be one or more storage servers and each storage server is connected to one or more non-volatile solid state memory units, which may be referred to as storage units or storage devices. One embodiment includes a single storage server in each storage node and between one to eight non-volatile solid state memory units, however this one example is not meant to be limiting. The storage server may include a processor, dynamic random access memory (DRAM) and interfaces for the internal communication bus and power distribution for each of the power buses. Inside the storage node, the interfaces and storage unit share a communication bus, e.g., PCI Express, in some embodiments. The non-volatile solid state memory units may directly access the internal communication bus interface through a storage node communication bus, or request the storage node to access the bus interface. The non-volatile solid state memory unit contains an embedded central processing unit (CPU), solid state storage controller, and a quantity of solid state mass storage, e.g., between 2-32 terabytes (TB) in some embodiments. An embedded volatile storage medium, such as DRAM, and an energy reserve apparatus are included in the non-volatile solid state memory unit. In some embodiments, the energy reserve apparatus is a capacitor, super-capacitor, or battery that enables transferring a subset of DRAM contents to a stable storage medium in the case of power loss. In some embodiments, the non-volatile solid state memory unit is constructed with a storage class memory, such as phase change or magnetoresistive random access memory (MRAM) that substitutes for DRAM and enables a reduced power hold-up apparatus.

One of many features of the storage nodes and non-volatile solid state storage is the ability to proactively rebuild data in a storage cluster. The storage nodes and non-volatile solid state storage can determine when a storage node or non-volatile solid state storage in the storage cluster is unreachable, independent of whether there is an attempt to read data involving that storage node or non-volatile solid state storage. The storage nodes and non-volatile solid state storage then cooperate to recover and rebuild the data in at least partially new locations. This constitutes a proactive rebuild, in that the system rebuilds data without waiting until the data is needed for a read access initiated from a client system employing the storage cluster. These and further details of the storage memory and operation thereof are discussed below.

FIG. 1 is a perspective view of a storage cluster 160, with multiple storage nodes 150 and internal solid-state memory coupled to each storage node to provide network attached storage or storage area network, in accordance with some embodiments. A network attached storage, storage area network, or a storage cluster, or other storage memory, could include one or more storage clusters 160, each having one or more storage nodes 150, in a flexible and reconfigurable arrangement of both the physical components and the amount of storage memory provided thereby. The storage cluster 160 is designed to fit in a rack, and one or more racks can be set up and populated as desired for the storage memory. The storage cluster 160 has a chassis 138 having multiple slots 142. It should be appreciated that chassis 138 may be referred to as a housing, enclosure, or rack unit. In one embodiment, the chassis 138 has fourteen slots 142, although other numbers of slots are readily devised. For example, some embodiments have four slots, eight slots, sixteen slots, thirty-two slots, or other suitable number of slots. Each slot 142 can accommodate one storage node 150 in some embodiments. Chassis 138 includes flaps 148 that can be utilized to mount the chassis 138 on a rack. Fans 144 provide air circulation for cooling of the storage nodes 150 and components thereof, although other cooling components could be used, or an embodiment could be devised without cooling components. A switch fabric 146 couples storage nodes 150 within chassis 138 together and to a network for communication to the memory. In an embodiment depicted in FIG. 1, the slots 142 to the left of the switch fabric 146 and fans 144 are shown occupied by storage nodes 150, while the slots 142 to the right of the switch fabric 146 and fans 144 are empty and available for insertion of storage node 150 for illustrative purposes. This configuration is one example, and one or more storage nodes 150 could occupy the slots 142 in various further arrangements. The storage node arrangements need not be sequential or adjacent in some embodiments. Storage nodes 150 are hot pluggable, meaning that a storage node 150 can be inserted into a slot 142 in the chassis 138, or removed from a slot 142, without stopping or powering down the system. Upon insertion or removal of storage node 150 from slot 142, the system automatically reconfigures in order to recognize and adapt to the change. Reconfiguration, in some embodiments, includes restoring redundancy and/or rebalancing data or load.

Each storage node 150 can have multiple components. In the embodiment shown here, the storage node 150 includes a printed circuit board 158 populated by a CPU 156, i.e., processor, a memory 154 coupled to the CPU 156, and a non-volatile solid state storage 152 coupled to the CPU 156, although other mountings and/or components could be used in further embodiments. The memory 154 has instructions which are executed by the CPU 156 and/or data operated on by the CPU 156. As further explained below, the non-volatile solid state storage 152 includes flash or, in further embodiments, other types of solid-state memory.

Referring to FIG. 1, storage cluster 160 is scalable, meaning that storage capacity with non-uniform storage sizes is readily added, as described above. One or more storage nodes 150 can be plugged into or removed from each chassis and the storage cluster self-configures in some embodiments. Plug-in storage nodes 150, whether installed in a chassis as delivered or later added, can have different sizes. For example, in one embodiment a storage node 150 can have any multiple of 4 TB, e.g., 8 TB, 12 TB, 16 TB, 32 TB, etc. In further embodiments, a storage node 150 could have any multiple of other storage amounts or capacities. Storage capacity of each storage node 150 is broadcast, and influences decisions of how to stripe the data. For maximum storage efficiency, an embodiment can self-configure as wide as possible in the stripe, subject to a predetermined requirement of continued operation with loss of up to one, or up to two, non-volatile solid state storage units 152 or storage nodes 150 within the chassis.

FIG. 2 is a block diagram showing a communications interconnect 170 and power distribution bus 172 coupling multiple storage nodes 150. Referring back to FIG. 1, the communications interconnect 170 can be included in or implemented with the switch fabric 146 in some embodiments. Where multiple storage clusters 160 occupy a rack, the communications interconnect 170 can be included in or implemented with a top of rack switch, in some embodiments. As illustrated in FIG. 2, storage cluster 160 is enclosed within a single chassis 138. External port 176 is coupled to storage nodes 150 through communications interconnect 170, while external port 174 is coupled directly to a storage node. External power port 178 is coupled to power distribution bus 172. Storage nodes 150 may include varying amounts and differing capacities of non-volatile solid state storage 152 as described with reference to FIG. 1. In addition, one or more storage nodes 150 may be a compute only storage node as illustrated in FIG. 2. Authorities 168 are implemented on the non-volatile solid state storages 152, for example as lists or other data structures stored in memory. In some embodiments the authorities are stored within the non-volatile solid state storage 152 and supported by software executing on a controller or other processor of the non-volatile solid state storage 152. In a further embodiment, authorities 168 are implemented on the storage nodes 150, for example as lists or other data structures stored in the memory 154 and supported by software executing on the CPU 156 of the storage node 150. Authorities 168 control how and where data is stored in the non-volatile solid state storages 152 in some embodiments. This control assists in determining which type of erasure coding scheme is applied to the data, and which storage nodes 150 have which portions of the data. Each authority 168 may be assigned to a non-volatile solid state storage 152. Each authority may control a range of inode numbers, segment numbers, or other data identifiers which are assigned to data by a file system, by the storage nodes 150, or by the non-volatile solid state storage 152, in various embodiments.

Every piece of data, and every piece of metadata, has redundancy in the system in some embodiments. In addition, every piece of data and every piece of metadata has an owner, which may be referred to as an authority. If that authority is unreachable, for example through failure of a storage node, there is a plan of succession for how to find that data or that metadata. In various embodiments, there are redundant copies of authorities 168. Authorities 168 have a relationship to storage nodes 150 and non-volatile solid state storage 152 in some embodiments. Each authority 168, covering a range of data segment numbers or other identifiers of the data, may be assigned to a specific non-volatile solid state storage 152. In some embodiments the authorities 168 for all of such ranges are distributed over the non-volatile solid state storages 152 of a storage cluster. Each storage node 150 has a network port that provides access to the non-volatile solid state storage(s) 152 of that storage node 150. Data can be stored in a segment, which is associated with a segment number and that segment number is an indirection for a configuration of a RAID (redundant array of independent disks) stripe in some embodiments. The assignment and use of the authorities 168 thus establishes an indirection to data. Indirection may be referred to as the ability to reference data indirectly, in this case via an authority 168, in accordance with some embodiments. A segment identifies a set of non-volatile solid state storage 152 and a local identifier into the set of non-volatile solid state storage 152 that may contain data. In some embodiments, the local identifier is an offset into the device and may be reused sequentially by multiple segments. In other embodiments the local identifier is unique for a specific segment and never reused. The offsets in the non-volatile solid state storage 152 are applied to locating data for writing to or reading from the non-volatile solid state storage 152 (in the form of a RAID stripe). Data is striped across multiple units of non-volatile solid state storage 152, which may include or be different from the non-volatile solid state storage 152 having the authority 168 for a particular data segment.

If there is a change in where a particular segment of data is located, e.g., during a data move or a data reconstruction, the authority 168 for that data segment should be consulted, at that non-volatile solid state storage 152 or storage node 150 having that authority 168. In order to locate a particular piece of data, embodiments calculate a hash value for a data segment or apply an inode number or a data segment number. The output of this operation points to a non-volatile solid state storage 152 having the authority 168 for that particular piece of data. In some embodiments there are two stages to this operation. The first stage maps an entity identifier (ID), e.g., a segment number, inode number, or directory number to an authority identifier. This mapping may include a calculation such as a hash or a bit mask. The second stage is mapping the authority identifier to a particular non-volatile solid state storage 152, which may be done through an explicit mapping. The operation is repeatable, so that when the calculation is performed, the result of the calculation repeatably and reliably points to a particular non-volatile solid state storage 152 having that authority 168. The operation may include the set of reachable storage nodes as input. If the set of reachable non-volatile solid state storage units changes the optimal set changes. In some embodiments, the persisted value is the current assignment (which is always true) and the calculated value is the target assignment the cluster will attempt to reconfigure towards. This calculation may be used to determine the optimal non-volatile solid state storage 152 for an authority in the presence of a set of non-volatile solid state storage 152 that are reachable and constitute the same cluster. The calculation also determines an ordered set of peer non-volatile solid state storage 152 that will also record the authority to non-volatile solid state storage mapping so that the authority may be determined even if the assigned non-volatile solid state storage is unreachable. A duplicate or substitute authority 168 may be consulted if a specific authority 168 is unavailable in some embodiments.

With reference to FIGS. 1 and 2, two of the many tasks of the CPU 156 on a storage node 150 are to break up write data, and reassemble read data. When the system has determined that data is to be written, the authority 168 for that data is located as above. When the segment ID for data is already determined the request to write is forwarded to the non-volatile solid state storage 152 currently determined to be the host of the authority 168 determined from the segment. The host CPU 156 of the storage node 150, on which the non-volatile solid state storage 152 and corresponding authority 168 reside, then breaks up or shards the data and transmits the data out to various non-volatile solid state storage 152. The transmitted data is written as a data stripe in accordance with an erasure coding scheme. In some embodiments, data is requested to be pulled, and in other embodiments, data is pushed. In reverse, when data is read, the authority 168 for the segment ID containing the data is located as described above. The host CPU 156 of the storage node 150 on which the non-volatile solid state storage 152 and corresponding authority 168 reside requests the data from the non-volatile solid state storage and corresponding storage nodes pointed to by the authority. In some embodiments the data is read from flash storage as a data stripe. The host CPU 156 of storage node 150 then reassembles the read data, correcting any errors (if present) according to the appropriate erasure coding scheme, and forwards the reassembled data to the network. In further embodiments, some or all of these tasks can be handled in the non-volatile solid state storage 152. In some embodiments, the segment host requests the data be sent to storage node 150 by requesting pages from storage and then sending the data to the storage node making the original request.

In some systems, for example in UNIX-style file systems, data is handled with an index node or inode, which specifies a data structure that represents an object in a file system. The object could be a file or a directory, for example. Metadata may accompany the object, as attributes such as permission data and a creation timestamp, among other attributes. A segment number could be assigned to all or a portion of such an object in a file system. In other systems, data segments are handled with a segment number assigned elsewhere. For purposes of discussion, the unit of distribution is an entity, and an entity can be a file, a directory or a segment. That is, entities are units of data or metadata stored by a storage system. Entities are grouped into sets called authorities. Each authority has an authority owner, which is a storage node that has the exclusive right to update the entities in the authority. In other words, a storage node contains the authority, and that the authority, in turn, contains entities.

A segment is a logical container of data in accordance with some embodiments. A segment is an address space between medium address space and physical flash locations, i.e., the data segment number, are in this address space. Segments may also contain meta-data, which enable data redundancy to be restored (rewritten to different flash locations or devices) without the involvement of higher level software. In one embodiment, an internal format of a segment contains client data and medium mappings to determine the position of that data. Each data segment is protected, e.g., from memory and other failures, by breaking the segment into a number of data and parity shards, where applicable. The data and parity shards are distributed, i.e., striped, across non-volatile solid state storage 152 coupled to the host CPUs 156 (See FIG. 5) in accordance with an erasure coding scheme. Usage of the term segments refers to the container and its place in the address space of segments in some embodiments. Usage of the term stripe refers to the same set of shards as a segment and includes how the shards are distributed along with redundancy or parity information in accordance with some embodiments.

A series of address-space transformations takes place across an entire storage system. At the top are the directory entries (file names) which link to an inode. Inodes point into medium address space, where data is logically stored. Medium addresses may be mapped through a series of indirect mediums to spread the load of large files, or implement data services like deduplication or snapshots. Medium addresses may be mapped through a series of indirect mediums to spread the load of large files, or implement data services like deduplication or snapshots. Segment addresses are then translated into physical flash locations. Physical flash locations have an address range bounded by the amount of flash in the system in accordance with some embodiments. Medium addresses and segment addresses are logical containers, and in some embodiments use a 128 bit or larger identifier so as to be practically infinite, with a likelihood of reuse calculated as longer than the expected life of the system. Addresses from logical containers are allocated in a hierarchical fashion in some embodiments. Initially, each non-volatile solid state storage unit 152 may be assigned a range of address space. Within this assigned range, the non-volatile solid state storage 152 is able to allocate addresses without synchronization with other non-volatile solid state storage 152.

Data and metadata is stored by a set of underlying storage layouts that are optimized for varying workload patterns and storage devices. These layouts incorporate multiple redundancy schemes, compression formats and index algorithms. Some of these layouts store information about authorities and authority masters, while others store file metadata and file data. The redundancy schemes include error correction codes that tolerate corrupted bits within a single storage device (such as a NAND flash chip), erasure codes that tolerate the failure of multiple storage nodes, and replication schemes that tolerate data center or regional failures. In some embodiments, low density parity check (LDPC) code is used within a single storage unit. Reed-Solomon encoding is used within a storage cluster, and mirroring is used within a storage grid in some embodiments. Metadata may be stored using an ordered log structured index (such as a Log Structured Merge Tree), and large data may not be stored in a log structured layout.

In order to maintain consistency across multiple copies of an entity, the storage nodes agree implicitly on two things through calculations: (1) the authority that contains the entity, and (2) the storage node that contains the authority. The assignment of entities to authorities can be done by pseudo randomly assigning entities to authorities, by splitting entities into ranges based upon an externally produced key, or by placing a single entity into each authority. Examples of pseudorandom schemes are linear hashing and the Replication Under Scalable Hashing (RUSH) family of hashes, including Controlled Replication Under Scalable Hashing (CRUSH). In some embodiments, pseudo-random assignment is utilized only for assigning authorities to nodes because the set of nodes can change. The set of authorities cannot change so any subjective function may be applied in these embodiments. Some placement schemes automatically place authorities on storage nodes, while other placement schemes rely on an explicit mapping of authorities to storage nodes. In some embodiments, a pseudorandom scheme is utilized to map from each authority to a set of candidate authority owners. A pseudorandom data distribution function related to CRUSH may assign authorities to storage nodes and create a list of where the authorities are assigned. Each storage node has a copy of the pseudorandom data distribution function, and can arrive at the same calculation for distributing, and later finding or locating an authority. Each of the pseudorandom schemes requires the reachable set of storage nodes as input in some embodiments in order to conclude the same target nodes. Once an entity has been placed in an authority, the entity may be stored on physical devices so that no expected failure will lead to unexpected data loss. In some embodiments, rebalancing algorithms attempt to store the copies of all entities within an authority in the same layout and on the same set of machines.

Examples of expected failures include device failures, stolen machines, datacenter fires, and regional disasters, such as nuclear or geological events. Different failures lead to different levels of acceptable data loss. In some embodiments, a stolen storage node impacts neither the security nor the reliability of the system, while depending on system configuration, a regional event could lead to no loss of data, a few seconds or minutes of lost updates, or even complete data loss.

In the embodiments, the placement of data for storage redundancy is independent of the placement of authorities for data consistency. In some embodiments, storage nodes that contain authorities do not contain any persistent storage. Instead, the storage nodes are connected to non-volatile solid state storage units that do not contain authorities. The communications interconnect between storage nodes and non-volatile solid state storage units consists of multiple communication technologies and has non-uniform performance and fault tolerance characteristics. In some embodiments, as mentioned above, non-volatile solid state storage units are connected to storage nodes via PCI express, storage nodes are connected together within a single chassis using Ethernet backplane, and chassis are connected together to form a storage cluster. Storage clusters are connected to clients using Ethernet or fiber channel in some embodiments. If multiple storage clusters are configured into a storage grid, the multiple storage clusters are connected using the Internet or other long-distance networking links, such as a “metro scale” link or private link that does not traverse the internet.

Authority owners have the exclusive right to modify entities, to migrate entities from one non-volatile solid state storage unit to another non-volatile solid state storage unit, and to add and remove copies of entities. This allows for maintaining the redundancy of the underlying data. When an authority owner fails, is going to be decommissioned, or is overloaded, the authority is transferred to a new storage node. Transient failures make it non-trivial to ensure that all non-faulty machines agree upon the new authority location. The ambiguity that arises due to transient failures can be achieved automatically by a consensus protocol such as Paxos, hot-warm failover schemes, via manual intervention by a remote system administrator, or by a local hardware administrator (such as by physically removing the failed machine from the cluster, or pressing a button on the failed machine). In some embodiments, a consensus protocol is used, and failover is automatic. If too many failures or replication events occur in too short a time period, the system goes into a self-preservation mode and halts replication and data movement activities until an administrator intervenes in accordance with some embodiments.

As authorities are transferred between storage nodes and authority owners update entities in their authorities, the system transfers messages between the storage nodes and non-volatile solid state storage units. With regard to persistent messages, messages that have different purposes are of different types. Depending on the type of the message, the system maintains different ordering and durability guarantees. As the persistent messages are being processed, the messages are temporarily stored in multiple durable and non-durable storage hardware technologies. In some embodiments, messages are stored in RAM, NVRAM and on NAND flash devices, and a variety of protocols are used in order to make efficient use of each storage medium. Latency-sensitive client requests may be persisted in replicated NVRAM, and then later NAND, while background rebalancing operations are persisted directly to NAND.

Persistent messages are persistently stored prior to being transmitted. This allows the system to continue to serve client requests despite failures and component replacement. Although many hardware components contain unique identifiers that are visible to system administrators, manufacturer, hardware supply chain and ongoing monitoring quality control infrastructure, applications running on top of the infrastructure address virtualize addresses. These virtualized addresses do not change over the lifetime of the storage system, regardless of component failures and replacements. This allows each component of the storage system to be replaced over time without reconfiguration or disruptions of client request processing.

In some embodiments, the virtualized addresses are stored with sufficient redundancy. A continuous monitoring system correlates hardware and software status and the hardware identifiers. This allows detection and prediction of failures due to faulty components and manufacturing details. The monitoring system also enables the proactive transfer of authorities and entities away from impacted devices before failure occurs by removing the component from the critical path in some embodiments.

FIG. 3 is a multiple level block diagram, showing contents of a storage node 150 and contents of a non-volatile solid state storage 152 of the storage node 150. Data is communicated to and from the storage node 150 by a network interface controller (NIC) 202 in some embodiments. Each storage node 150 has a CPU 156, and one or more non-volatile solid state storage 152, as discussed above. Moving down one level in FIG. 3, each non-volatile solid state storage 152 has a relatively fast non-volatile solid state memory, such as nonvolatile random access memory (NVRAM) 204, and flash memory 206. In some embodiments, NVRAM 204 may be a component that does not require program/erase cycles (DRAM, MRAM, PCM), and can be a memory that can support being written vastly more often than the memory is read from. Moving down another level in FIG. 3, the NVRAM 204 is implemented in one embodiment as high speed volatile memory, such as dynamic random access memory (DRAM) 216, backed up by energy reserve 218. Energy reserve 218 provides sufficient electrical power to keep the DRAM 216 powered long enough for contents to be transferred to the flash memory 206 in the event of power failure. In some embodiments, energy reserve 218 is a capacitor, super-capacitor, battery, or other device, that supplies a suitable supply of energy sufficient to enable the transfer of the contents of DRAM 216 to a stable storage medium in the case of power loss. The flash memory 206 is implemented as multiple flash dies 222, which may be referred to as packages of flash dies 222 or an array of flash dies 222. It should be appreciated that the flash dies 222 could be packaged in any number of ways, with a single die per package, multiple dies per package (i.e. multichip packages), in hybrid packages, as bare dies on a printed circuit board or other substrate, as encapsulated dies, etc. In the embodiment shown, the non-volatile solid state storage 152 has a controller 212 or other processor, and an input output (I/O) port 210 coupled to the controller 212. I/O port 210 is coupled to the CPU 156 and/or the network interface controller 202 of the flash storage node 150. Flash input output (I/O) port 220 is coupled to the flash dies 222, and a direct memory access unit (DMA) 214 is coupled to the controller 212, the DRAM 216 and the flash dies 222. In the embodiment shown, the I/O port 210, controller 212, DMA unit 214 and flash I/O port 220 are implemented on a programmable logic device (PLD) 208, e.g., a field programmable gate array (FPGA). In this embodiment, each flash die 222 has pages, organized as sixteen kB (kilobyte) pages 224, and a register 226 through which data can be written to or read from the flash die 222. In further embodiments, other types of solid-state memory are used in place of, or in addition to flash memory illustrated within flash die 222.

Storage clusters 160, in various embodiments as disclosed herein, can be contrasted with storage arrays in general. The storage nodes 150 are part of a collection that creates the storage cluster 160. Each storage node 150 owns a slice of data and computing required to provide the data. Multiple storage nodes 150 cooperate to store and retrieve the data. Storage memory or storage devices, as used in storage arrays in general, are less involved with processing and manipulating the data. Storage memory or storage devices in a storage array receive commands to read, write, or erase data. The storage memory or storage devices in a storage array are not aware of a larger system in which they are embedded, or what the data means. Storage memory or storage devices in storage arrays can include various types of storage memory, such as RAM, solid state drives, hard disk drives, etc. The storage units 152 described herein have multiple interfaces active simultaneously and serving multiple purposes. In some embodiments, some of the functionality of a storage node 150 is shifted into a storage unit 152, transforming the storage unit 152 into a combination of storage unit 152 and storage node 150. Placing computing (relative to storage data) into the storage unit 152 places this computing closer to the data itself. The various system embodiments have a hierarchy of storage node layers with different capabilities. By contrast, in a storage array, a controller owns and knows everything about all of the data that the controller manages in a shelf or storage devices. In a storage cluster 160, as described herein, multiple controllers in multiple storage units 152 and/or storage nodes 150 cooperate in various ways (e.g., for erasure coding, data sharing, metadata communication and redundancy, storage capacity expansion or contraction, data recovery, and so on).

FIG. 4 shows a storage server environment, which uses embodiments of the storage nodes 150 and storage units 152 of FIGS. 1-3. In this version, each storage unit 152 has a processor such as controller 212 (see FIG. 3), an FPGA (field programmable gate array), flash memory 206, and NVRAM 204 (which is super-capacitor backed DRAM 216, see FIGS. 2 and 3) on a PCIe (peripheral component interconnect express) board in a chassis 138 (see FIG. 1). The storage unit 152 may be implemented as a single board containing storage, and may be the largest tolerable failure domain inside the chassis. In some embodiments, up to two storage units 152 may fail and the device will continue with no data loss.

The physical storage is divided into named regions based on application usage in some embodiments. The NVRAM 204 is a contiguous block of reserved memory in the storage unit 152 DRAM 216, and is backed by NAND flash. NVRAM 204 is logically divided into multiple memory regions written for two as spool (e.g., spool_region). Space within the NVRAM 204 spools is managed by each authority 512 independently. Each device provides an amount of storage space to each authority 512. That authority 512 further manages lifetimes and allocations within that space. Examples of a spool include distributed transactions or notions. When the primary power to a storage unit 152 fails, onboard super-capacitors provide a short duration of power hold up. During this holdup interval, the contents of the NVRAM 204 are flushed to flash memory 206. On the next power-on, the contents of the NVRAM 204 are recovered from the flash memory 206.

As for the storage unit controller, the responsibility of the logical “controller” is distributed across each of the blades containing authorities 512. This distribution of logical control is shown in FIG. 4 as a host controller 402, mid-tier controller 404 and storage unit controller(s) 406. Management of the control plane and the storage plane are treated independently, although parts may be physically co-located on the same blade. Each authority 512 effectively serves as an independent controller. Each authority 512 provides its own data and metadata structures, its own background workers, and maintains its own lifecycle.

FIG. 5 is a blade 502 hardware block diagram, showing a control plane 504, compute and storage planes 506, 508, and authorities 512 interacting with underlying physical resources, using embodiments of the storage nodes 150 and storage units 152 of FIGS. 1-3 in the storage server environment of FIG. 4. The control plane 504 is partitioned into a number of authorities 512 which can use the compute resources in the compute plane 506 to run on any of the blades 502. The storage plane 508 is partitioned into a set of devices, each of which provides access to flash 206 and NVRAM 204 resources.

In the compute and storage planes 506, 508 of FIG. 5, the authorities 512 interact with the underlying physical resources (i.e., devices). From the point of view of an authority 512, its resources are striped over all of the physical devices. From the point of view of a device, it provides resources to all authorities 512, irrespective of where the authorities happen to run. Each authority 512 has allocated or has been allocated one or more partitions 510 of storage memory in the storage units 152, e.g. partitions 510 in flash memory 206 and NVRAM 204. Each authority 512 uses those allocated partitions 510 that belong to it, for writing or reading user data. Authorities can be associated with differing amounts of physical storage of the system. For example, one authority 512 could have a larger number of partitions 510 or larger sized partitions 510 in one or more storage units 152 than one or more other authorities 512.

FIG. 6 depicts elasticity software layers in blades 502 of a storage cluster 160, in accordance with some embodiments. In the elasticity structure, elasticity software is symmetric, i.e., each blade's 502 compute module 602 runs the three identical layers of processes depicted in FIG. 6. Storage managers 606 execute read and write requests from other blades 502 for data and metadata stored in local storage unit 152 NVRAM 204 and flash 206. Authorities 168 fulfill client requests by issuing the necessary reads and writes to the blades 502 on whose storage units 152 the corresponding data or metadata resides. Endpoints 604 parse client connection requests received from switch fabric 146 supervisory software, relay the client connection requests to the authorities 168 responsible for fulfillment, and relay the authorities' 168 responses to clients. The symmetric three-layer structure enables the storage system's high degree of concurrency. Elasticity scales out efficiently and reliably. In addition, elasticity implements a novel scale-out technique that balances work evenly across all resources regardless of client access pattern, and maximizes concurrency by eliminating much of the need for inter-blade coordination that typically occurs with conventional distributed locking.

Authorities 168 running in blade 502 compute modules 602 perform the internal operations required to fulfill client requests. One feature of elasticity is that authorities 168 are stateless, i.e., they cache active data and metadata in their own blades' 168 DRAMs for fast access, but they store every update in their NVRAM 204 partitions on three separate blades 502 until the update has been written to flash 206. All the storage system writes to NVRAM 204 are in triplicate to partitions on three separate blades 502. With triple-mirrored NVRAM 204 and persistent storage protected by parity and Reed-Solomon RAID checksums, the storage system can survive concurrent failure of two blades 502 with no loss of data, metadata, or access to either.

Because authorities 168 are stateless, they can migrate between blades 502. Each authority 168 has a unique identifier. NVRAM 204 and flash 206 partitions are associated with authorities' 168 identifiers, not with the blades 502 on which they are running. Thus, when an authority 168 migrates, the authority 168 continues to manage the same storage partitions from its new location. When a new blade 502 is installed in an embodiment of the storage cluster 160, the system automatically rebalances load by:

-   -   Partitioning the new blade's 502 storage for use by the system's         authorities 168,     -   Migrating selected authorities 168 to the new blade 502,     -   Starting endpoints 604 on the new blade 502 and including them         in the switch fabric's 146 client connection distribution         algorithm.

From their new locations, migrated authorities 168 persist the contents of their NVRAM 204 partitions on flash 206, process read and write requests from other authorities 168, and fulfill the client requests that endpoints 604 direct to them. Similarly, if a blade 502 fails or is removed, the system redistributes its authorities 168 among the system's remaining blades 502. The redistributed authorities 168 continue to perform their original functions from their new locations.

FIG. 7 depicts authorities 168 and storage resources in blades 502 of a storage cluster 160, in accordance with some embodiments. Each storage cluster 160 authority 168 is exclusively responsible for a partition of the flash 206 and NVRAM 204 on each blade 502. The authority 168 manages the content and integrity of its partitions independently of other authorities 168. Authorities 168 compress incoming data and preserve it temporarily in their NVRAM 204 partitions, and then consolidate, RAID-protect, and persist the data in segments of the storage in their flash 206 partitions. As the authorities 168 write data to flash 206, storage managers 606 perform the necessary flash translation to optimize write performance and maximize media longevity. In the background, authorities 168 “garbage collect,” or reclaim space occupied by data that clients have made obsolete by overwriting it. Because authorities' 168 partitions are disjoint, there is no need for distributed locking to execute client and writes or to perform background functions.

FIG. 8 shows a write process selector 802 that selects a process from among multiple write processes 804, to satisfy a data write request 806, in accordance with some embodiments. Upon receipt of the data write request 806, the write process selector 802 evaluates the write request 806 according to one or more rules 808, and selects a write process 812, 814, 816 from among the write processes 804. An execution unit 810 performs the selected write process 812, 814, 816. Write processes 804 could involve writing to NVRAM 204 and/or direct write to flash memory 206, bypassing NVRAM. A background write process flushes data from NVRAM 204 to flash memory 206. NVRAM 204 is supported by an energy reserve 208, as described above with reference to FIG. 3.

For implementation of the write process selector 802, the write processes 804 could be as sections of software, firmware and/or hardware, with rules 808 in a data structure or embedded in software or firmware or even in hardware. The write process selector 802 and execution unit 810 could be as software executing on a processor, firmware and/or hardware. By selecting from multiple write processes 804, the write process selector 802 tailors write request handling to the length or type of data, arrival rate of data, arrival of data in series or parallel, or other characteristic of data, for system efficiency. In some embodiments, the rules 808 are dynamic and reconfigurable, for example through downloading new rules to a data structure, or reprogramming a programmable logic device. There could be one write process selector 802 per blade 502, e.g., in the compute module 602 in the storage node 150 with the CPU 156 (see FIG. 3), or one per storage unit 152, e.g., in the controller 212 and/or associated programmable logic device 208 (see FIG. 3) or other circuitry of the storage unit 152, in various embodiments.

FIG. 9 depicts multiple write processes 812, 814, 816 (from multiple write processes 804) and background write process 902, suitable for use in the write process selector 802 of FIG. 8. These write processes relate to how data or metadata is written by the authorities 168 in the compute modules 602 of the blades 502 into the NVRAM 204 and the flash memory 206 in the storage units 152. In some cases, it is most efficient to write data into the NVRAM 204, for example striped in RAID stripes that span the blades 502 as depicted in FIG. 7, and have a background write process 902 flush data from the NVRAM 204 to the flash memory 206. In other cases, it is more efficient to write data directly to flash memory 206, bypassing the NVRAM 204 but again striped in RAID stripes that span the blades 502 as depicted in FIG. 7. Numbering of the write processes described herein is arbitrary, and the total number of write processes used by the write process selector 802 could be fixed or variable and greater than or equal to two. A subset, or superset, of these write processes could be used. The write processes depicted herein could be used for other conditions besides those described below.

The first write process 812 is selected, in some embodiments, in response to the data write request 806 being for less than a threshold amount of data, i.e., a small write. For a small write, the write process is to lock the inode of the file for which the data is being written, update the inode (see FIG. 10), transfer the data into the NVRAM 204, and unlock the inode. Here, the inode is updated and the data is transferred into NVRAM as foreground processes, with the inode locked so that any other write process cannot attempt to update the inode or transfer data, relating to that inode, into memory. The background write process 902 flushes the data from the NVRAM 204 to the flash memory 206.

A foreground task is one that should be performed in sequence, in parallel or in line with any actions that are visible to a client. A background task is one that can be performed immediately, or later, but which does not necessarily need to be performed prior to an action that is visible to a client (e.g., an acknowledgment, reply or other response to the client). Background tasks are not in the critical path, and foreground tasks are in a critical path with actions visible to the client.

The second write process 814 is selected, in some embodiments, in response to the data write request 806 being for greater than a threshold amount of data, and for a serial write of data, i.e., not parallel writes. For a large, serial write of data, the write process is to transfer the data into NVRAM 204, lock the inode, update the inode, commit the data (see FIG. 11), and unlock the inode. In this write process, the data is transferred into NVRAM prior to locking the inode. The inode is updated and the data is committed, with the inode locked, again so that other write processes cannot attempt to update the inode or commit their data in interference with the inode updating and data committing underway. The background write process 902 flushes the data from the NVRAM 204 to the flash memory 206.

The third write process 816 is selected, in some embodiments, in response to the data write request 806 being for greater than a threshold amount of data and the data being written in parallel writes. For a large, parallel write of data, the write process is to transfer the data directly to flash memory 206, bypassing the NVRAM 204, lock the inode, update the inode, commit the data, and unlock the inode. In this write process, the data is transferred to flash memory prior to locking the inode. The inode is updated and the data is committed, with the inode locked, again so that other write processes cannot attempt to update the inode or commit their data in interference with the inode updating and data committing underway. There is no need, in the third write process 816, for a background write process to flush data from NVRAM 204 to the flash memory 206, since the data is written directly to the flash memory 206.

Comparison of the second and third write processes 814, 816 reveals why the third write process 816 is more efficient for a large number of parallel writes of data involving the same inode. Applying the second write process for such a large number of parallel writes would tie up the NVRAM and create a bottleneck with the multiple updates to the inode, one for each of the parallel writes. Also, all of the other parallel writes would wait while one of the parallel writes locks and updates the inode, since they could not commit their data until the one write unlocks the inode again. By having all of the parallel writes transfer data directly into flash memory 206, and then having only one locking and updating of the inode with data commitment, this bottleneck situation is relieved and the third write process 806 becomes more efficient for a large number of parallel writes.

Conversely, the second write process 814 is more efficient for a large serial write of data, since writing to NVRAM 204 is quicker than writing to flash memory 206. The slower writes to flash memory 206 can take place in background. Comparison of the first and second write processes 812, 814 shows that a small write can be accomplished efficiently by transferring data into NVRAM 204 with the inode locked, since this does not tie up the inode for a long period of time. A larger, serial write is accomplished efficiently by transferring data into the NVRAM 204 prior to locking the inode for the inode update and data committing, since this does not tie up the inode for a long period of time as would occur if the large transfer of data into NVRAM 204 were to be done with the inode locked.

The second and third write processes 814, 816 could be combined into a fourth write process 904 with conditional transfer, in one embodiment. This fourth write process 904 replaces the second and third write processes 814, 816, in an embodiment where the write process selector 802 selects between the first write process 814 and the fourth write process 904. The fourth write process 904 is selected, in some embodiments, responsive to the data write request 806 being for greater than a threshold amount of data, i.e., a large write. For a large write of data, the write process is to transfer the data into the storage system, conditionally as a provisional write into the NVRAM 204 for serial writes and to the flash memory 206 for parallel writes, lock the inode, update the inode, commit the data, and unlock the inode. In this write process, the data is transferred into the storage system prior to locking the inode. The inode is updated and the data is committed, with the inode locked, so that other write processes cannot attempt to update the inode or commit their data in interference with the inode updating and data committing underway. The background write process 902 flushes data from NVRAM 204 to the flash memory 206.

Various embodiments of storage systems could use the first write process 812 and the fourth write process 904, the first write process 812 and the second write process 814, the first write process 812 and the third write process 816, the first write process 812, second write process 814 and third write process 816, the second write process 814 and the third write process 816, any of these with some other write process(es), or other combinations of write processes.

FIG. 10 shows an inode 1002 with a lock 1004, suitable for use in the write processes of FIGS. 8 and 9. The inode 1002 with lock 1004 can be implemented as metadata in the storage system, for example as replicated metadata in NVRAM 204 in multiple storage units 152 and blades 502 for redundancy. The inode 1002 for a file has file information 1006, such as filename, file extent, permissions, a modification timestamp, etc., and a lock 1004, which could be implemented as one or more bits, bytes or other amount of data. One value of the lock indicates the lock is locked, another that the lock is unlocked, and further data could indicate the owner (e.g., an authority 168 owner of an inode) of the lock when the lock is taken, i.e., locked. Various mechanisms for lock consistency and coherency could be applied, so that it is not possible for two authorities 168 to take the lock at the same time.

FIG. 11 depicts a file extent lookaside as a data structure 1102 suitable for use with the write processes of FIGS. 8 and 9. In some embodiments, the file extent lookaside is implemented as part of the metadata in the inode 1002, and is subject to locking and unlocking by the lock 1004 of the inode 1002. A file log 1104, for example shown as the log for the file “abc”, is included in the file extent lookaside data structure 1102. This example file log is shown for an extent of data from 0 to 16 MB. Over time, portions of data spanning various ranges within the extent of the data are logged in the file extent lookaside. Some of these ranges of data may overlap. Committing the data, in a write process 814, 816, 904, involves writing to the file extent lookaside, to record the range of data that is committed. A background process resolves data overwrites through the file extent lookaside. Resolution of data overwrites is depicted symbolically as the vertical dashed lines of newly added ranges of data projecting downward onto older ranges of data, producing obsoleted data where newer data overwrites older data. Overwritten data is subject to background garbage collection, so that flash memory 206 occupied by the obsoleted data can be consolidated and block erased for reuse. Committing the data converts the data from a provisional write to an allowed write or a persistent write. Data that is written into NVRAM 204 or flash memory 206 outside of the inode locking is provisionally written data, or provisional data, until the data is committed by writing to the file extent lookaside, with the inode locked.

FIG. 12 is a flow diagram of a method for adaptive concurrency for write persistence, which can be practiced in the storage cluster of FIGS. 1-7, using the write process selector of FIGS. 8-11, in accordance with some embodiments. Some or all of the actions in the method can be performed by various processors, such as processors in storage nodes or processors in storage units. In an action 1202, a write request is received into the storage system, for example from a client. The write request is evaluated, based on rules, in an action 1204. These rules specify write processes for various aspects of data or write requests, and could be kept in a database or built into software, hardware or firmware. In some embodiments, the rules are dynamic and can be updated, for example with new thresholds or new selection criteria, instructions or other directions for write processes.

In an action 1206, a write process is selected from among multiple write processes, based on the evaluation. Several write processes are shown in FIG. 9, for consideration as candidates for a group of write processes. Data is written into the storage system according to the selected write process, in an action 1208. Efficiencies of writing data to NVRAM, for background flushing to flash, or writing directly to flash, are possible considerations for selecting a write process. Operation of an inode lock, and which operations to perform with or without the inode locked, are other possible considerations for selecting a write process. Selected write processes operate adaptively and concurrently across storage nodes and storage units of the storage cluster, with write persistence for the data.

It should be appreciated that the methods described herein may be performed with a digital processing system, such as a conventional, general-purpose computer system. Special purpose computers, which are designed or programmed to perform only one function may be used in the alternative. FIG. 13 is an illustration showing an exemplary computing device which may implement the embodiments described herein. The computing device of FIG. 13 may be used to perform embodiments of the functionality for adaptive concurrency for write persistence in accordance with some embodiments. The computing device includes a central processing unit (CPU) 1301, which is coupled through a bus 1305 to a memory 1303, and mass storage device 1307. Mass storage device 1307 represents a persistent data storage device such as a floppy disc drive or a fixed disc drive, which may be local or remote in some embodiments. The mass storage device 1307 could implement a backup storage, in some embodiments. Memory 1303 may include read only memory, random access memory, etc. Applications resident on the computing device may be stored on or accessed via a computer readable medium such as memory 1303 or mass storage device 1307 in some embodiments. Applications may also be in the form of modulated electronic signals modulated accessed via a network modem or other network interface of the computing device. It should be appreciated that CPU 1301 may be embodied in a general-purpose processor, a special purpose processor, or a specially programmed logic device in some embodiments.

Display 1311 is in communication with CPU 1301, memory 1303, and mass storage device 1307, through bus 1305. Display 1311 is configured to display any visualization tools or reports associated with the system described herein. Input/output device 1309 is coupled to bus 1305 in order to communicate information in command selections to CPU 1301. It should be appreciated that data to and from external devices may be communicated through the input/output device 1309. CPU 1301 can be defined to execute the functionality described herein to enable the functionality described with reference to FIGS. 1-12. The code embodying this functionality may be stored within memory 1303 or mass storage device 1307 for execution by a processor such as CPU 1301 in some embodiments. The operating system on the computing device may be iOS™, MS-WINDOWS™, OS/2™, UNIX™, LINUX™, or other known operating systems. It should be appreciated that the embodiments described herein may also be integrated with a virtualized computing system implemented with physical computing resources.

It should be understood that although the terms first, second, etc. may be used herein to describe various steps or calculations, these steps or calculations should not be limited by these terms. These terms are only used to distinguish one step or calculation from another. For example, a first calculation could be termed a second calculation, and, similarly, a second step could be termed a first step, without departing from the scope of this disclosure. As used herein, the term “and/or” and the “/” symbol includes any and all combinations of one or more of the associated listed items.

As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises”, “comprising”, “includes”, and/or “including”, when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Therefore, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting.

It should also be noted that in some alternative implementations, the functions/acts noted may occur out of the order noted in the figures. For example, two figures shown in succession may in fact be executed substantially concurrently or may sometimes be executed in the reverse order, depending upon the functionality/acts involved.

With the above embodiments in mind, it should be understood that the embodiments might employ various computer-implemented operations involving data stored in computer systems. These operations are those requiring physical manipulation of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. Further, the manipulations performed are often referred to in terms, such as producing, identifying, determining, or comparing. Any of the operations described herein that form part of the embodiments are useful machine operations. The embodiments also relate to a device or an apparatus for performing these operations. The apparatus can be specially constructed for the required purpose, or the apparatus can be a general-purpose computer selectively activated or configured by a computer program stored in the computer. In particular, various general-purpose machines can be used with computer programs written in accordance with the teachings herein, or it may be more convenient to construct a more specialized apparatus to perform the required operations.

A module, an application, a layer, an agent or other method-operable entity could be implemented as hardware, firmware, or a processor executing software, or combinations thereof. It should be appreciated that, where a software-based embodiment is disclosed herein, the software can be embodied in a physical machine such as a controller. For example, a controller could include a first module and a second module. A controller could be configured to perform various actions, e.g., of a method, an application, a layer or an agent.

The embodiments can also be embodied as computer readable code on a non-transitory computer readable medium. The computer readable medium is any data storage device that can store data, which can be thereafter read by a computer system. Examples of the computer readable medium include hard drives, network attached storage (NAS), read-only memory, random-access memory, CD-ROMs, CD-Rs, CD-RWs, magnetic tapes, and other optical and non-optical data storage devices. The computer readable medium can also be distributed over a network coupled computer system so that the computer readable code is stored and executed in a distributed fashion. Embodiments described herein may be practiced with various computer system configurations including hand-held devices, tablets, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers and the like. The embodiments can also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a wire-based or wireless network.

Although the method operations were described in a specific order, it should be understood that other operations may be performed in between described operations, described operations may be adjusted so that they occur at slightly different times or the described operations may be distributed in a system which allows the occurrence of the processing operations at various intervals associated with the processing.

In various embodiments, one or more portions of the methods and mechanisms described herein may form part of a cloud-computing environment. In such embodiments, resources may be provided over the Internet as services according to one or more various models. Such models may include Infrastructure as a Service (IaaS), Platform as a Service (PaaS), and Software as a Service (SaaS). In IaaS, computer infrastructure is delivered as a service. In such a case, the computing equipment is generally owned and operated by the service provider. In the PaaS model, software tools and underlying equipment used by developers to develop software solutions may be provided as a service and hosted by the service provider. SaaS typically includes a service provider licensing software as a service on demand. The service provider may host the software, or may deploy the software to a customer for a given period of time. Numerous combinations of the above models are possible and are contemplated.

Various units, circuits, or other components may be described or claimed as “configured to” or “configurable to” perform a task or tasks. In such contexts, the phrase “configured to” or “configurable to” is used to connote structure by indicating that the units/circuits/components include structure (e.g., circuitry) that performs the task or tasks during operation. As such, the unit/circuit/component can be said to be configured to perform the task, or configurable to perform the task, even when the specified unit/circuit/component is not currently operational (e.g., is not on). The units/circuits/components used with the “configured to” or “configurable to” language include hardware—for example, circuits, memory storing program instructions executable to implement the operation, etc. Reciting that a unit/circuit/component is “configured to” perform one or more tasks, or is “configurable to” perform one or more tasks, is expressly intended not to invoke 35 U.S.C. 112, sixth paragraph, for that unit/circuit/component. Additionally, “configured to” or “configurable to” can include generic structure (e.g., generic circuitry) that is manipulated by software and/or firmware (e.g., an FPGA or a general-purpose processor executing software) to operate in manner that is capable of performing the task(s) at issue. “Configured to” may also include adapting a manufacturing process (e.g., a semiconductor fabrication facility) to fabricate devices (e.g., integrated circuits) that are adapted to implement or perform one or more tasks. “Configurable to” is expressly intended not to apply to blank media, an unprogrammed processor or unprogrammed generic computer, or an unprogrammed programmable logic device, programmable gate array, or other unprogrammed device, unless accompanied by programmed media that confers the ability to the unprogrammed device to be configured to perform the disclosed function(s).

The foregoing description, for the purpose of explanation, has been described with reference to specific embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The embodiments were chosen and described in order to best explain the principles of the embodiments and its practical applications, to thereby enable others skilled in the art to best utilize the embodiments and various modifications as may be suited to the particular use contemplated. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims. 

What is claimed is:
 1. A method comprising: selecting a write process from among a plurality of write processes that specify writing to differing types of memory inside and outside of an inode lock, responsive to receiving a write request for writing data into a storage system, wherein the write process is selected based, at least in part, on one or more of a size of the data to be written into the storage system and whether the write request is for a serial or parallel write, and wherein each write process in the plurality of write processes indicates when an inode associated with file information of the data is locked and when the inode associated with the file information of the data is unlocked, relative to a type of memory and relative to when the data is to be written to the type of memory in the storage system; and writing the data into the storage system in accordance with the selected write process, wherein one of the plurality of write processes comprises: transferring the data into the storage system with the inode unlocked; locking the inode associated with file information of the data in the memory; updating the file information in the inode while the inode is locked; committing the data while the inode is locked; and unlocking the inode.
 2. The method of claim 1, wherein selecting the write process comprises choosing a first write process, responsive to the data in the write request being less than a threshold amount of data, the first write process comprising: updating the inode, in non-volatile random access memory (NVRAM) while the inode is locked for transfer of the data into the NVRAM, wherein a background write process is to flush the data from the NVRAM to flash memory.
 3. The method of claim 1, wherein selecting the write process comprises choosing a second write process, responsive to the data in the write request being greater than a threshold amount of data and the write request being for a serial write, the second write process comprising: updating the inode, in the NVRAM while the inode is locked to commit the data in the NVRAM, wherein the data is transferred into the NVRAM prior to the locking the inode, and wherein a background write process is to flush the data from the NVRAM to flash memory.
 4. The method of claim 1, wherein selecting the write process comprises choosing a third write process, responsive to the data in the write request being greater than a threshold amount of data and the write request being for a plurality of parallel writes, the third write process comprising: transferring the data to flash memory of the storage system, bypassing NVRAM, prior to the locking the inode, wherein the inode is updated and the data is committed with the inode locked.
 5. The method of claim 1, wherein: the transferring the data into the storage system comprises writing the data to NVRAM as a foreground process prior to the locking the inode, and flushing the data from the NVRAM to flash memory of the storage system, as a background process.
 6. The method of claim 1, wherein: the transferring the data into the storage system comprises writing the data to flash memory of the storage system as a foreground process prior to the locking the inode, bypassing NVRAM.
 7. The method of claim 1, wherein the committing the data comprises writing to a data structure in NVRAM, and further comprising: resolving data overwrites, through the data structure, as a background process.
 8. A tangible, non-transitory, computer-readable media having instructions thereupon which, when executed by a processor, cause the processor to perform a method comprising: receiving a write request for writing data into a storage system; selecting a write process from among a plurality of write processes that specify writing to differing types of memory inside and outside of an inode lock, based, at least in part, on one or more of a size of the data to be written into the storage system and whether the write request is for a serial or parallel write, wherein each write process in the plurality of write processes indicates when an inode associated with file information of the data is locked and when the inode associated with the file information of the data is unlocked, relative to a type of memory and relative to when the data is to be written to the type of memory in the storage system; and writing the data into the storage system according to the selected write process, wherein one of the plurality of write processes comprises: transferring the data into the storage system with the inode unlocked; locking the inode associated with file information of the data in memory; updating the file information in the inode while the inode is locked; and committing the data while the inode is locked; and unlocking the inode.
 9. The computer-readable media of claim 8, wherein selecting the write process comprises choosing a first write process, responsive to the data in the write request being less than a threshold amount of data; and the first write process comprises: updating the inode in NVRAM while the inode is locked to transfer the data into the NVRAM, wherein a background write process is to flush the data from the NVRAM to flash memory.
 10. The computer-readable media of claim 8, wherein selecting the write process comprises choosing a second write process, responsive to the data in the write request being greater than a threshold amount of data and wherein the write request is for a serial write; and the second write process comprises; updating the inode in the NVRAM while the inode is locked to commit the data in the NVRAM, wherein the data is transferred into the NVRAM prior to the locking the inode, and wherein a background write process is to flush the data from the NVRAM to flash memory.
 11. The computer-readable media of claim 8, wherein: selecting the write process comprises choosing a third write process, responsive to the data in the write request being greater than a threshold amount of data and wherein the write request is for a plurality of parallel writes; and the third write process comprises; updating the inode in the NVRAM while the inode is locked to commit the data in the NVRAM.
 12. The computer-readable media of claim 8, wherein: the committing the data is executed in the NVRAM and comprises converting the write to an allowed write and wherein the method further comprises flushing the data from the NVRAM to flash memory of the storage system, as a background process.
 13. The computer-readable media of claim 8, wherein: the transferring the data into the storage system comprises writing the data to flash memory of the storage system, bypassing the NVRAM and wherein the committing the data is executed in the NVRAM and comprises converting the write to an allowed write.
 14. The computer-readable media of claim 8, wherein the committing the data comprises writing to a file extent lookaside data structure in the NVRAM, and wherein the method further comprises a background process of resolving data overwrites through the file extent lookaside data structure.
 15. A storage system, comprising: non-volatile random access memory (NVRAM); flash memory; and one or more processors, configurable to: select a write process from among a plurality of write processes that specify writing to differing types of memory inside and outside of inode lock, responsive to receiving a request to write data into the storage system, the write process selected based, at least in part, on one or more of a size of the data to be written into the storage system and whether the write request is for a serial or parallel write, and wherein each write process in the plurality of write processes indicates when an inode associated with file information of the data is locked and when the inode associated with the file information of the data is unlocked, relative to a type of memory and relative to when the data is to be written to the type of memory in the storage system, and write the data into the storage system in accordance with the selected write process, with one of the plurality of write processes comprising: transferring the data into the storage system with the inode unlocked; locking the inode associated with file information of the data; updating the inode, in the NVRAM, while the inode is locked; committing the data, in the NVRAM, while the inode is locked; and unlocking the inode.
 16. The storage system of claim 15, wherein the one or more processors are configurable to select a first write process responsive to a request to write less than a threshold amount of data into the storage system, with the first write process comprising: updating the inode, in the NVRAM, while the inode is locked to transfer the data into the NVRAM.
 17. The storage system of claim 15, wherein the one or more processors are configurable to select a second write process responsive to a request to write more than a threshold amount of data, in serial form, into the storage system, with the second write process comprising: updating the inode, in the NVRAM, while the inode is locked to commit the data in the NVRAM, wherein the data is transferred into the NVRAM prior to the locking the inode.
 18. The storage system of claim 15, wherein the one or more processors are configurable to select a third write process responsive to a request to write more than a threshold amount of data, in parallel writes, into the storage system, with the third write process comprising: updating the inode, in the NVRAM, while the inode is locked to commit the data in the NVRAM, wherein the data is transferred to flash memory prior to the locking the inode.
 19. The storage system of claim 15, wherein the one or more processors are configurable to flush the data from the NVRAM to the flash memory, as a background process.
 20. The storage system of claim 15, wherein the NVRAM comprises an energy reserve coupled to random access memory (RAM) and wherein the RAM is configurable to hold a data structure for the committing the data. 